ChipAgents, the category leader in agentic AI platforms for semiconductor design, announced the expansion of its AI-native engineering platform across digital and analog chip design, bringing more of the semiconductor development flow onto a shared agentic foundation.

AI models are evolving on a months-long cadence, while traditional chip development can take 12–18 months or longer. Building the next generation of custom silicon for AI requires engineering teams to move faster across increasingly complex digital and analog design cycles. Yet much of that work still happens across fragmented tools, teams and workflows, forcing engineers to manually carry context from one stage of the design process to the next.

ChipAgents’ full-stack approach enables engineers to define objectives, constraints and critical judgment calls while AI agents carry more of the execution forward, reasoning over design context, operating engineering tools, evaluating results and determining the next action toward closure.

“Autonomous semiconductor engineering is a systems problem,” said William Wang, founder and CEO of ChipAgents. “It is not enough to make an individual model stronger or add more agents to a workflow. The AI needs to understand the organization’s design knowledge, coordinate the right models and tools, evaluate real engineering results and account for the physical consequences of each decision. We built ChipAgents around that entire system so engineers can focus on the design objective while AI handles more of the execution underneath.”

Powering the platform is IC-star, ChipAgents’ chip neural engine for digital and analog semiconductor engineering. IC-star is designed to navigate the enormous semiconductor design space by evaluating the current design state and determining the next best action rather than requiring engineers to manually decide which model, tool or workflow to run next.

IC-star brings together four tightly integrated capabilities:

  • IC Design Ontology: A persistent context layer for engineers and agents that unifies design knowledge, plans, reusable skills and customer-specific methodologies, continuously improving the system through engineering feedback.

  • Reasoning Core: Plans and coordinates agents, models and engineering tools around an objective to execute long-horizon workflows such as root-cause analysis, PPA-aware RTL closure and analog layout generation.

  • Multiphysics-Aware Models: Predict timing, PPA, DRC, DFT and analog physical design to enable multi-objective co-optimization at generation time. Renoir, ChipAgents’ semiconductor-specific, physics-aware LLM, serves as a core domain model within this layer.

  • Design-Driven Model Navigator: Dynamically routes work across AI models based on the task, balancing quality of results, time to results and cost.

Together, those capabilities allow ChipAgents to co-optimize model choice, token consumption, tool execution, engineering review and physical feedback around the total engineering outcome, rather than optimizing each AI task independently. ChipAgents measures value in the time it takes for designs to converge, engineering effort and overall execution costs across both digital and analog chip design.

The same foundation spans both digital and analog engineering. Digital workflows supported by ChipAgents include specification analysis, architecture exploration, RTL design, functional and formal verification, root-cause analysis and debug, coverage closure and PPA-aware optimization. Analog workflows extend across topology and schematic design, simulation, behavioral modeling, layout generation and physical verification.

ChipAgents is expanding its collaboration with NVIDIA to fine-tune Nemotron models for AI-native digital and analog design workflows. ChipAgents reports initial results show that the post-trained Nemotron model achieves performance competitive with frontier models, including Fable 5.1 and GPT-6 Astra, based on open benchmarks, while delivering the highest performance and best cost efficiency among the open-weight models evaluated. These results mark a meaningful step toward AI that can carry engineering intent from specification through physical implementation, making autonomous chip design more reliable and practical for engineering teams.

“For Ambiq, advancing ultra-low-power design means optimizing power, performance, and area together. ChipAgents’ IC-star brings multi-objective optimization to our digital design workflows, helping us accelerate RTL development, test case generation, and root cause analysis,” said Scott Hanson, founder and CTO of Ambiq. “Security is a fundamental requirement for us, and ChipAgents’ focus on protecting sensitive data and IP is essential to enabling AI-native flows in our engineering environment.”

Analog design presents a particularly challenging environment for AI because engineering decisions depend on circuit behavior, waveforms and physical tradeoffs that cannot be captured through code generation alone. By connecting agentic execution with design context and physics-aware models, ChipAgents can create dynamically programmable autonomous workflows in which AI generates, simulates, evaluates and iterates while engineers retain control over requirements and signoff.

“IC design demands deep engineering expertise and meticulous attention to detail. Over the past year, we have worked with ChipAgents to bring AI into our development workflows, creating a foundation that blends engineering knowledge with AI-powered assistance across the IC design lifecycle,” said Dave Brownell, vice president of engineering enablement at Analog Devices. “We see tremendous potential to build on this foundation, helping our teams accelerate development and focus more of their expertise on delivering innovative, high-performance products.”

“We are adopting ChipAgents to accelerate our chip and IP design and verification workflows,” said Simon Blake-Wilson, senior vice president and general manager of silicon IP at Rambus. “By combining Rambus’ deep semiconductor and silicon IP expertise with ChipAgents’ IC-star engine, we see an opportunity to help our customers bring advanced chips to market faster and achieve better design outcomes within their preferred design environments.”

“The opportunity for agentic AI is to turn a chip team’s accumulated design knowledge into the ability to explore more ideas, learn from simulation and resolve engineering tradeoffs faster,” said Tim Costa, vice president and general manager of industrial and computational engineering at NVIDIA. “Pairing specialized NVIDIA Nemotron models with ChipAgents’ physics-aware workflows can shift the engineer’s role from managing each tool run to directing a design strategy, with agents translating simulation and verification feedback into the next design decision.”

The expanded platform builds on more than 200 semiconductor enterprise deployments across a growing range of design and verification workflows. Recent deployments illustrate the measurable impact of moving AI deeper into semiconductor engineering. Andes Technology reduced one processor-verification workflow from two to three months to approximately three weeks and shortened a processor customization project by 30%. eMemory reduced engineering effort for datasheet analysis and verification-testbench construction by approximately 80%. Whalechip reduced semiconductor root-cause analysis from days to approximately 15–60 minutes per round while identifying four critical bugs.

ChipAgents integrates securely with customers’ existing tools and workflows, whether deployed on-premises or in the cloud. The architecture preserves organizational knowledge and supports on-premises self-improvement for organizations requiring greater control over proprietary design data.

ChipAgents will provide a deeper technical look at the IC-star engine and its application across digital and analog design during an Oct. 29 webinar.

Register for the Oct. 29 webinar here: https://chipagents.ai/events/IC-star-webinar-2026

About ChipAgents

ChipAgents is a leading agentic AI platform for semiconductor engineering, providing end-to-end automation for complex digital and analog chip design, verification and debugging workflows. The platform combines semiconductor-specific intelligence, autonomous agents and AI-native tools to accelerate chip development and improve productivity. Founded in 2024, ChipAgents serves semiconductor companies worldwide and is headquartered in Santa Clara, California. For more information, visit chipagents.ai.

FAQ

What is IC-star? IC-star is the chip neural engine powering the ChipAgents platform. It brings together organizational design context, reasoning and agent orchestration, dynamic model routing and physics-aware models so AI can determine and execute the next best action toward an engineering objective.

What does “full-stack” mean for ChipAgents? Full stack means ChipAgents coordinates more than individual AI agents. The platform connects customer design knowledge, agentic workflows, AI models, engineering tools, compute and physical feedback so those elements can be optimized together around time to a verified result, engineering effort and execution cost.

Does ChipAgents support both digital and analog chip engineering? Yes. ChipAgents uses a common IC-star foundation across supported digital and analog workflows. Digital capabilities include RTL design, verification, debug, coverage closure and PPA-aware optimization, while analog capabilities include schematic design, behavioral modeling, simulation, layout generation and physical verification.

Does ChipAgents replace existing tools? No. ChipAgents is designed to fit into existing semiconductor engineering environments. IC-star coordinates AI models, agents and established engineering tools, allowing teams to automate more of the work between them without replacing proven design, verification and signoff infrastructure.

How widely is ChipAgents being used? ChipAgents has more than 200 semiconductor enterprise deployments across design and verification workflows, with customers reporting measurable improvements in engineering cycle time, verification and debugging.

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